1. Field of the Invention
The present invention relates to a method of driving a plasma display device and a plasma display device and, more particularly, to a method of driving a three-electrode surface-discharge plasma display device.
2. Description of the Related Art
AC-driven plasma display panels (PDPs) have conventionally received a great deal of attention as next-generation displays replacing CRTs because the PDPs are self-emission-type displays excellent in visibility and they also allow display on large thin screens. Particularly, surface-discharge PDPs are expected as displays compatible with high-definition digital broadcasting due to their larger screen size and are required to have an image quality higher than CRTs.
AC-driven PDPs are classified into two-electrode type PDPs which perform selective discharge (address discharge) and sustain discharge using two electrodes and three-electrode type PDPs which perform address discharge using a third electrode. The three-electrode types PDPs are further classified into a type with the third electrode formed on a substrate on which the first and second electrodes for performing sustain discharge are laid out and a type with the third electrode formed on another substrate opposite to the substrate of the first and second electrodes.
All types of the above PDP devices are based on the same operation principle. The arrangement of a PDP device in which the first and second electrodes for performing sustain discharge are formed on the first substrate, and the third electrode is formed on said second substrate opposite to the first substrate will be described below.
FIG. 10 is a view showing the overall arrangement of an AC-driven PDP device. In the AC-driven PDP device shown in FIG. 10, a plurality of cells each corresponding to one pixel of a display image are arrayed in a matrix. FIG. 10 shows an AC-driven PDP device having cells arrayed in a matrix with m rows by n columns. The AC-driven PDP also has scanning electrodes Y1 to Yn and common electrodes X, which are formed to run parallel on the first substrate, and address electrodes A1 to Am which are formed on said second substrate opposite to the first substrate so as to run perpendicular to the electrodes Y1 to Yn and X. The common electrodes X are formed in proximities of the scanning electrodes Y1 to Yn in correspondence with them and commonly connected at terminals on one side.
The common terminal of the common electrodes X is connected to the output terminal of an X-side circuit 2. The scanning electrodes Y1 to Yn are connected to the output terminals of a Y-side circuit 3. The address electrodes A1 to Am are connected to the output terminals of an address-side circuit 4. The X-side circuit 2 is formed from a circuit for repeating discharge. The Y-side circuit 3 is formed from a circuit for performing line-sequential scanning and a circuit for repeating discharge. The address-side circuit 4 is formed from a circuit for selecting a column to be displayed.
The X-side circuit 2, Y-side circuit 3, and address-side circuit 4 are controlled by control signals supplied from a drive control circuit 5. That is, a cell to be turned on is determined by the address-side circuit 4 and the line-sequential scanning circuit in the Y-side circuit 3, and discharge repeats itself by the X-side circuit 2 and Y-side circuit 3, thereby performing the display operation of the PDP.
The control circuit 5 generates the control signals on the basis of display data D from an external device, a clock CLK indicating the read timing of the display data D, a horizontal sync signal HS, and a vertical sync signal VS and supplies the control signals to the X-side circuit 2, Y-side circuit 3, and address-side circuit 4.
FIG. 11A is a sectional view of a cell Cij as a pixel, which is in the ith row and jth column. Referring to FIG. 11A, the common electrode X and the scanning electrode Yi are formed on a front glass substrate 11. The electrodes are coated with a dielectric layer 12 that insulates the electrodes from a discharge space 17. The dielectric layer 12 is coated with an MgO (magnesium oxide) protective film 13.
On the other hand, the address electrode Aj is formed on a back glass substrate 14 opposite to the front glass substrate 11. The address electrode Aj is coated with a dielectric layer 15, and the dielectric layer 15 is coated with a phosphor 18. Ne+Xe Penning gas is sealed in the discharge space 17 between the MgO protective film 13 and the dielectric layer 15.
FIG. 11B is a view for explaining the capacitance of a cell that performs sustain discharge in the AC-driven PDP. As shown in FIG. 11B, in the AC-driven PDP, capacitive components Ca, Cb, and Cc are present in the discharge space 17, between the common electrode X and the scanning electrode Y, and in the front glass substrate 11, respectively. A capacitance Cpcell per cell between sustain discharge electrodes is determined by the sum of the capacitive components (Cpcell=Ca+Cb+Cc). The sum of capacitances Cpcell of cells between all sustain discharge electrodes corresponds to the capacitance of the cells that perform sustain discharge in the entire panel.
FIG. 11C is a view for explaining light emission of the AC-driven PDP. As shown in FIG. 11C, stripe-shaped red, blue, and green phosphors 18 are laid out and applied to the inner surfaces of ribs 16. The phosphors 18 are excited by discharge between the common electrode X and the scanning electrode Y so as to emit light.
FIG. 12 is a timing chart showing a conventional method of driving an AC-driven PDP. This timing chart shows a so-called “address/sustain-discharge-period-separation-type write address scheme”. In the timing chart of FIG. 12, one of a plurality of subfields of one frame is shown. One subfield is divided into a reset period comprised of a full write period and full erase period, an address period, and a sustain discharge period.
In the reset period, all the scanning electrodes Y1 to Yn are set at ground level (0 V), and simultaneously, a full write pulse having a voltage Vs+Vw (about 400 V) is applied to the common electrodes X. At this time, all the address electrodes A1 to Am have a potential Vaw (about 100 V). Consequently, discharge occurs in all cells of all display lines to generate wall charges independently of the preceding display state.
Next, the potentials of the common electrodes X and address electrodes A1 to Am change to 0 V. As the voltage of wall charges themselves exceeds the discharge start voltage in all cells, discharge starts. In this discharge, no wall charges are formed because the electrodes have no potential difference. Space charges neutralize by themselves to end the discharge, i.e., so-called self-erase discharge occurs. With this self-erase discharge, all cells in the panel are set in a uniform state free from wall charges. The reset period acts to set all cells in the same state independently of the ON/OFF state of each cell in the preceding subfield. This makes it possible to stably perform the subsequent address (write) discharge.
In the address period, address discharge is line-sequentially performed to turn on/off each cell in accordance with display data. First, a voltage of −Vy level (about −150 V) is applied to the scanning electrode Y1 corresponding to the first display line, and a voltage of −Vsc level (about −50 V) is applied to the scanning electrodes Y2 to Yn corresponding to the remaining display lines. At the same time, an address pulse having a voltage Va (about 50 V) is selectively applied to the address electrode Aj corresponding to a cell which should cause sustain discharge, i.e., a cell to be turned on in the address electrodes A1 to Am.
As a result, discharge occurs between the scanning electrode Y1 and the address electrode Aj of the cell to be turned on. With this priming (pilot flame), discharge between the scanning electrode Y1 and the common electrode X having a voltage Vx (about 50 V) immediately starts. With this discharge, wall charges in an amount enough for the next sustain discharge are accumulated on the surface of the MgO protective film 13 on the common electrode X and scanning electrode Y1 of the selected cell. For the scanning electrodes Y2 to Yn corresponding to the remaining display lines as well, the voltage of −Vy is sequentially applied to a scanning electrode corresponding to a selected cell, and the voltage of −Vsc level is applied to a scanning electrode corresponding to each of remaining, unselected cells. With this processing, new display data is written in all display lines.
In the subsequent sustain discharge period, a sustain pulse having a voltage Vs (about 200 V) is alternately applied to the scanning electrodes Y1 to Yn and common electrodes X to perform sustain discharge so that an image of one subfield is displayed. In the “address/sustain-discharge-period-separation-type write address scheme”, the luminance of the image is determined by the length of the sustain discharge period, i.e., the number of times of sustain pulse application.
FIG. 13 is a view showing the structure of one frame. FIG. 13 shows the structure of one frame for 16-level display as an example of grayscale display.
Referring to FIG. 13, one frame is formed from four subfields SF1, SF2, SF3, and SF4. The subfields SF1 to SF4 are comprised of reset periods RS1 to RS4, address periods AD1 to AD4, and sustain discharge periods SU1 to SU4, respectively. The reset periods RS1 to RS4 or address periods AD1 to AD4 of the subfields SF1 to SF4 have equal lengths.
The lengths of the sustain discharge periods SU1 to SU4 are set to SU1: SU2: SU3: SU4=1: 2: 4: 8. Hence, when a subfield in which cells are to be turned on is selected from the subfields SF1 to SF4, grayscale display with 16 gray levels from 0 to 15 can be performed. Note that the OFF period is a period without any drive waveform output.
FIGS. 14A and 14B are views showing the arrangement of a surface-discharge PDP. FIGS. 14A and 14B show the arrangement of a plasma display which causes discharge between all sustain discharge electrodes (X- and Y-electrodes) to display an image.
FIG. 14A is a schematic view showing the arrangement of a surface-discharge PDP. A surface-discharge PDP 20 has X-electrodes X1 to X5 and Y-electrodes Y1 to Y4, which are formed on one substrate to run parallel to each other, and address electrodes A1 to A6 which are formed on the other substrate to run perpendicular to the X-electrodes X1 to X5 and Y-electrodes Y1 to Y4. The surface-discharge PDP 20 has partitions 21 to 27 formed parallel to the address electrodes A1 to A6 to partition discharge spaces.
In this surface-discharge PDP 20, cells are formed in regions where the X-electrodes X1 to X5 and Y-electrodes Y1 to Y4 adjoin each other and the address electrodes A1 to A6 run perpendicular to the X- and Y-electrodes. The cells can be represented by display lines L1 to L8 between the sustain discharge electrodes (X- and Y-electrodes), as shown in FIG. 14A.
FIG. 14B is a sectional view of the surface-discharge PDP. FIG. 14B shows a section perpendicular to the X- and Y-electrodes and parallel to the address electrodes. Referring to FIG. 14B, reference numeral 28 denotes a back substrate on which the address electrodes are formed; and 29, a front substrate on which the X- and Y-electrodes are formed. As described above, in the surface-discharge PDP, cells are formed in regions where the X- and Y-electrodes adjoin each other and the address electrodes A1 to A6 run perpendicular to the X- and Y-electrodes, and discharge occurs in regions D1 to D3, as shown in FIG. 14B. That is, discharge is caused between all sustain discharge electrodes (X- and Y-electrodes) to display an image.
FIG. 15 is a view showing the structure of a frame of the surface-discharge PDP. FIG. 15 shows a frame structure when discharge is caused between all sustain discharge electrodes (X- and Y-electrodes) to display an image.
Referring to FIG. 15, one frame is formed from first and second fields. For example, display is performed on odd-numbered display lines in the first field and on even-numbered display lines in the second field, thereby displaying one frame. Each of the first and second fields has a plurality of (e.g., eight) subfields. Each subfield has the same frame structure as that shown in FIG. 13, and a description thereof will be omitted.
FIG. 16 is a timing chart showing an example of the drive waveforms of the surface-discharge PDP. FIG. 16 shows drive waveforms in the first field where discharge is performed between an X-electrode Xi and a Y-electrode Yi (i is an arbitrary integer) to display an image and, more specifically, drive waveforms in one of a plurality of subfields of the first field. One subfield is divided into a reset period comprised of a full write period and full erase period, an address period, and a sustain discharge period.
FIG. 16 shows the drive waveforms of an arbitrary address electrode A, X-electrodes X1 and X2, and Y-electrodes Y1 and Y2. For the remaining X- and Y-electrodes, each set of two X-electrodes and two Y-electrodes (X-electrode X3, Y-electrode Y3, X-electrode X4, and Y-electrode Y4), (X-electrode X5, Y-electrode Y5, X-electrode X6, and Y-electrode Y6), . . . is driven by the same drive waveforms as those shown in FIG. 16.
In the reset period, first, a voltage (−Vq) is applied to the X-electrodes X1 and X2, and a voltage Vws is applied to the Y-electrodes Y1 and Y2. With this operation, discharge occurs in all cells of all display lines to form wall charges independently of the preceding display state. At this time, the voltage applied to the Y-electrodes Y1 and Y2 has a waveform that continuously changes along with the elapse of time (this waveform will be referred to as a “ramp wave” hereinafter). When such a ramp wave is applied, discharge sequentially occurs in cells that have reached the discharge voltage during the rise of the ramp wave. Actually, an optimum voltage (voltage almost equal to the discharge start voltage) is applied to each cell.
Next, the voltage Vx is applied to the X-electrodes X1 and X2, and a ramp wave whose final voltage is the voltage (−Vy) is applied to the Y-electrodes Y1 and Y2. As the voltage of wall charges themselves exceeds the discharge start voltage in all cells, discharge starts. At this time as well, weak discharge occurs in accordance with application of the ramp wave, so the accumulated wall charges are erased with some exceptions.
In the address period, address discharge is line-sequentially performed to turn on/off each cell in accordance with display data. The address period is divided into the first half portion and second half portion. At the first half portion in the address period, address discharge is performed for odd-numbered Y-electrodes. At the second half portion in the address period, address discharge is performed for even-numbered Y-electrodes.
In this address period, the voltage (−Vy) is applied to the Y-electrode selected for address discharge, and a voltage (−Vy+Vsc) is applied to the remaining Y-electrodes. At the same time, an address pulse having the voltage Va is selectively applied to the address electrode A corresponding to a cell which should cause sustain discharge, i.e., a cell to be turned on. As a result, discharge occurs between the Y-electrode and the address electrode A of the cell to be turned on. With this priming (pilot flame), discharge between the Y-electrode and the X-electrode having the voltage Vx starts, and wall charges in an amount enough for sustain discharge are accumulated.
FIG. 16 shows only address discharge for the Y-electrodes Y1 and Y2. At the first half portion in the address period, the Y-electrodes Y1, Y3, Y5, . . . are sequentially selected in this order for address discharge. At the second half portion in the address period, the Y-electrodes Y2, Y4, Y6, . . . are sequentially selected in this order for address discharge.
In the subsequent sustain discharge period, a sustain pulse having the voltage Vs is alternately applied to the X- and Y-electrodes at appropriate timings to perform sustain discharge, thereby displaying an image of one subfield.
However, to drive a surface-discharge PDP by the above-described drive method, drive voltages according to the timing chart shown in FIG. 16 must be applied to the respective electrodes, and each element of the surface-discharge PDP driving device must have a high breakdown voltage. For example, the circuit for applying the sustain pulse Vs shown in FIG. 16 to the X- and Y-electrodes must be constructed using elements having a very high breakdown voltage corresponding to the sustain pulse voltage.
As a solution to this problem, a surface-discharge PDP driving method has been proposed, in which in performing discharge between the sustain discharge electrodes of a surface-discharge PDP, a positive voltage is applied to one electrode, and a negative voltage is applied to the other electrode, thereby causing discharge between the electrodes using the potential difference between the electrodes without increasing the power consumption.
FIG. 17 is a timing chart showing an example of the drive waveforms of a surface-discharge PDP which performs discharge between electrodes using the potential difference between the electrodes. In the reset and address periods shown in FIG. 17, the X- and Y-electrodes have the same potential relationship as that shown in the timing chart of FIG. 16, and only the values of voltages to be applied to the electrodes are different.
In the sustain discharge period, voltages between (−Vs/2) and Vs/2 are applied to the X- and Y-electrodes. When the positive voltage Vs/2 is applied to one electrode, the negative voltage (−Vs/2) is applied to the other electrode. The potential difference between the X-electrode and the Y-electrode corresponds to the sustain pulse Vs shown in FIG. 16, so sustain discharge occurs between the sustain discharge electrodes (X- and Y-electrodes).
As described above, in the sustain discharge period, a positive voltage is applied to one electrode, and a negative voltage is applied to the other electrode in accordance with the drive waveforms shown in FIG. 17 whereby a potential difference corresponding to the sustain pulse Vs shown in FIG. 16 is generated between the sustain discharge electrodes (X- and Y-electrodes). With this arrangement, the breakdown voltage of each element of the driving device can be made lower as compared to a case wherein a surface-discharge PDP is driven in accordance with the drive waveforms shown in FIG. 16.
However, when voltages are applied to the X- and Y-electrodes in accordance with the drive waveforms shown in FIG. 17, wall charges remain on the address electrode A after the end of the sustain discharge period, as shown in FIG. 18.
FIG. 18 is a view showing wall charges formed on the respective electrodes (address electrode, X-electrodes Xi, and Y-electrodes Yi) after the end of the sustain discharge period. FIG. 18 shows wall charges formed on the respective electrodes when the sustain pulse voltage Vs/2 is last applied to the X-electrodes Xi and the sustain pulse voltage (−Vs/2) is last applied to the Y-electrodes Yi in the sustain discharge period.
As shown in FIG. 18, at the end of the sustain discharge period, negative wall charges are formed on the X-electrodes Xi (X1, X2, and X3 in FIG. 18) to which the voltage Vs/2 is applied, and positive wall charges are formed on the Y-electrodes Yi (Y1 and Y2 in FIG. 18) to which the voltage (−Vs/2) is applied. In addition, positive wall charges are formed at portions of the address electrode at the GND potential, which correspond to the X-electrodes Xi, and negative wall charges are formed at portions of the address electrode, which correspond to the Y-electrodes Yi.
If wall charges are formed on the address electrode after the end of the sustain discharge period, charges with opposite polarities are formed on address electrodes, X-electrodes, and Y-electrodes of neighboring cells in addressing (selecting cells to be turned on) in the next subfield. In addressing in the second next subfield, even when the address pulse Va is applied to the address electrode in accordance with display data, the potential difference between the address electrode and the Y-electrode may not reach the discharge voltage due to the residual charges, and address discharge between the address electrode and the Y-electrode may not occur. For example, if cells are repeatedly turned on/off in the respective subfields, as shown in FIG. 19, cells 31 and 32 which are supposed to be turned on in the subfield SF2 may not be turned on.
Conversely, if wall charges remain on the address electrode after the end of the sustain discharge period, the potential difference between the address electrode and the Y-electrode may reach the discharge voltage even when the address pulse Va is not applied to the address electrode, and address discharge may occur between the address electrode and the Y-electrode for a cell that is supposed to be kept off.
That is, when wall charges remain on the address electrode after the end of the sustain discharge period, in selecting (addressing) a cell to be turned on in the address period, the cell to be turned on cannot be accurately selected in accordance with display data. This degrades the drive margin or display quality of the PDP.